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Teaching Scheme |
Exam Scheme |
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Th. |
Pract. |
Total |
Th. |
Pract. |
TW/Viva |
Total |
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04 Marks |
02 Marks |
06 Marks |
100 Marks |
25 Marks |
25 Marks |
150 Marks |
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Hrs./Week |
Hrs./Week |
Hrs./Week |
(3 Hrs.) |
(3 Hrs.) |
(3 Hrs.) |
(3 Hrs.) |
Evolution of computer systems
Manual v/s machine computation, mechanical computer, electro-mechanical computer, evolution of electronic computer systems, introduction to three generations of computers, improvement in memory subsystems, controller design, parallel processing, operating systems, computer networks futures generation, different types of computer systems and their interfaces, complexity of computing.
Central Processing unit
Data path and control path : Data movement, arithmetic operations, logical operations. micro-operations on data path and the associated control signals : memory transfer, bus transfer, inter-register transfer, arithmetic micro operations, logic micro-operations.
Machine language instructions :
Instruction repertoires, trade-off between CISC and RISC.
Arithmetic and logic unit :
Arithmetic and logic unit, bit sliced ALU
Arithmetic processor :
Arithmetic processor as a coprocessor, arithmetic processor as an auxiliary processor.
Controller design.
Introduction : Functions of controller. control transfer : instruction control transfer, program control transfer. instruction interpretation and execution : brief introduction to hardwired control and micro-programmed control.
Memory Subsystem
CPU-Memory interaction : Impact of memory speed on CPU's processing power, processing power of CPU, Main storage speed and capacity vs CPU power. memory array organization and technology : 2D-organization, 3D-organization, 2.5-D organization.
Solution for the speed mismatch between main storage and CPU :
Memory hierarchy, working principle of cache, memory, address mapping schemes viz. Direct mapping, Associative mapping, block-set associative mapping.
Multiple module memory :
Comparison between single memory unit and multiple memory unit, its organization.
Associative memory : CAM and its working principle.
Virtual memory :
General hierarchical memory system and VM, logical vs. physical address space, working principle, different types of mapping schemes employed for VM environment.
Input-Output Processing :
Data transfer techniques : Data transfer mode, data transfer control, synchronous data transfer, asynchronous data transfer.
Bus Interface :
Parallel bus standards, serial communication standards, current loops, RS 232C standards, modems.
IO Accessing and data transfer :
Programmed IO, MPU initiated unconditional IO data transfer, MPU initiated conditional IO transfer, DMA.
IO Interrupt :
Daisy chaining priority scheme, polling scheme, independent interrupt request, vectored interrupt, interrupt handling on multi-bus.
Computer system architecture
Introduction : Layered view of a computer system.
Performance and cost : System performance, system cost.
Instruction set architecture (ISA) : Introduction, qualitative analysis of ISA, operand storage, addressing modes, program control instructions, ISA and compiler technology, organized compiler and optimization of instruction and register usage, quantitative analysis of ISA, reduced instruction set computer (RISC) architecture, instruction pipelining, load delay slot.
Filling, branch delay slot filling, case studies, ISA and operating systems, relative performance of primitive OS functions, inter-process communication, virtual memory organization, support for multiprocessing, micro-architecture.
Architecture of memory subsystem :
Memory hierarchy, cache memory, impact of associatively on cache misses, cache performance evaluation, reduction of miss penalty for read, reduced miss penalty for write, enhancing the speed of write operation, reducing miss penalty wit two level caches, operation of cache memory in virtual memory environment, unified vs separate data and instruction cache, unified vs separate data and instruction cache, cache coherence, extension of memory hierarchy, instruction pre-fetch buffer, register bank, complete hierarchy of memory subsystem.
IO Subsystem architecture :
IO Subsystem performance measure, design of IO subsystem, architecture of IO bus, SCSI Bus, ISA Bus architecture, PCI Bus, Micro-channel architecture. parallel processing system architecture : models of computation, classification of parallel processing system architecture, data flow architecture, reduction machine, parallel architecture for control driven machines, parallel processing machine based on SISD and MISD models, pipelined processor with instruction pipeline, pipeline hazards, pipeline scheduling, parallel processing systems based on SIMD model, multiprocessing system architecture based on MIMD mode, bus oriented systems, crossbar switched systems, microprocessor with single and multistage interconnection network (MIN), switch lattice architecture, directly interconnected MIMD system architecture, key issues of multiprocessing e.g. cache coherence, multiprocessor software.
Reference Book :
Computer organization and design -By P. Pal Chaudhary, PHI - second edition